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preliminary cy7c1061g/cy7c1061ge 16-mbit (1 m words 16 bit) static ram with error-correcting code (ecc) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-81540 rev. *k revised september 18, 2014 16-mbit (1 m words 16 bit) static ram with error-correcting code (ecc) features high speed ? t aa = 10 ns/15 ns embedded error-correcting code (ecc) for single-bit error correction low active and standby currents ? i cc = 90-ma typical at 100 mhz ? i sb2 = 20-ma typical operating voltage range: 1.65 v to 2.2 v, 2.2 v to 3.6 v, and 4.5 v to 5.5 v 1.0-v data retention transistor-transistor logic (ttl) compatible inputs and outputs error indication (err) pin to indicate 1-bit error detection and correction available in pb-free 48-pin tsop i, 54-pin tsop ii, and 48-ball vfbga packages functional description cy7c1061g and cy7c1061ge ar e high-performance cmos fast static ram devices with embedded ecc [1] . both devices are offered in single and dual chip enable options and in multiple pin configurations. the cy7c1061ge device includes an err pin that signals a single-bit error-detection and correction event during a read cycle. to access devices with a single ch ip enable input, assert the chip enable (ce ) input low. to access dual chip enable devices, assert both chip enable inputs ? ce 1 as low and ce 2 as high. to perform data writes, assert the write enable (we ) input low, and provide the data and address on the device data pins (i/o 0 through i/o 15 ) and address pins (a 0 through a 19 ) respectively. the byte high and byte low enable (bhe , ble ) inputs control byte writes, and write data on the corresponding i/o lines to the memory location specified. bhe controls i/o 8 through i/o 15 and ble controls i/o 0 through i/o 7 . to perform data reads, assert the output enable (oe ) input and provide the required address on the address lines. read data is accessible on i/o lines (i/o 0 through i/o 15 ). you can perform byte accesses by asserting the required byte enable signal (bhe or ble ) to read either the upper byte or the lower byte of data from the specified address location. all i/os (i/o 0 through i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high for a single chip enable device and ce 1 high / ce 2 low for a dual chip enable device), or control signals are de-asserted (oe , ble , bhe ). on the cy7c1061ge devices, the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the err output (err = high). see the truth table on page 16 for a complete description of read and write modes. the logic block diagrams are on page 2. the cy7c1061g and cy7c1061ge devices are available in 48-pin tsop i, 54-pin tsop ii, and 48-ball vfbga packages. product portfolio product features and options (see the pin configurations section) range v cc range (v) speed (ns) 10/15 current consumption operating i cc , (ma) standby, i sb2 ( m a) f = f max typ [2] max typ [2] max cy7c1061g18 single or dual chip enables optional err pins address msb a 19 pin placement options compatible with cypress and other vendors industrial 1.65 v?2.2 v 15 70 80 20 30 cy7c1061g(e)30 2.2 v?3.6 v 10 90 110 cy7c1061g 4.5 v?5.5 v 10 90 110 notes 1. this device does not support automatic write-back on error detection. 2. typical values are included only for reference and are not guaranteed or tested. typical values are measured at v cc = 1.8 v (for a v cc range of 1.65 v?2.2 v), v cc = 3 v (for a v cc range of 2.2 v?3.6 v), and v cc = 5 v (for a v cc range of 4.5 v?5.5 v), t a = 25 c.
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 2 of 27 logic block diagram ? cy7c1061g logic block diagram ? cy7c1061ge
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 3 of 27 contents pin configurations ........................................................... 4 maximum ratings............................................................. 7 operating range............................................................... 7 dc electrical characteristics .......................................... 7 capacitance ...................................................................... 8 thermal resistance.......................................................... 8 ac test loads and waveforms....................................... 8 data retention characteristics ....................................... 9 data retention waveform................................................ 9 ac switching characteristics ....................................... 10 switching waveforms .................................................... 11 truth table ...................................................................... 16 err output ? cy7c1061ge .......................................... 16 ordering information...................................................... 17 ordering code definitions ......................................... 17 package diagrams.......................................................... 18 acronyms ........................................................................ 21 document conventions ................................................. 21 units of measure ....................................................... 21 errata ............................................................................... 22 part numbers affected .............................................. 22 fast sram[44] qualification status........................ 22 fast sram[44] errata summa ry............................. 22 ac switching characteristics .................................... 23 document history page ................................................. 24 sales, solutions, and legal information ...................... 27 worldwide sales and design supp ort............. .......... 27 products .................................................................... 27 psoc? solutions ...................................................... 27 cypress developer community................................. 27 technical support .................. ................................... 27
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 4 of 27 pin configurations figure 1. 48-ball vfbga (6 8 1.0 mm) dual chip enable without err, address msb a19 at ball g2, cy7c1061g [3] package/grade id: bvjxi figure 2. 48-ball vfbga (6 8 1.0 mm) dual chip enable without err, address msb a19 at ball h6, cy7c1061g [3] package/grade id: bvxi figure 3. 48-ball vfbga (6 8 1.0 mm) single chip enable without err, address msb a19 at ball g2, cy7c1061g [3] package/grade id: bv1xi we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc a 18 a 19 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss note 3. nc pins are not connected internally to the die.
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 5 of 27 figure 4. 48-ball vfbga (6 8 1.0 mm) single chip enable with err, address msb a19 at ball g2 cy7c1061ge [4, 5] package/grade id: bv1xi figure 5. 48-ball vfbga (6 8 1.0 mm) dual chip enable with err, address msb a19 at ball g2 cy7c1061ge [4, 5] package/grade id: bvjxi figure 6. 48-ball vfbga (6 8 1.0 mm) dual chip enable with err, ad dress msb a19 at ball h6 cy7c1061ge [4, 5] package/grade id: bvxi pin configurations (continued) we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe err a 17 a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 err v cc v cc v ss we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc a 18 a 19 3 26 5 4 1 d e b a c f g h a 16 err v cc v cc v ss notes 4. nc pins are not connected internally to the die. 5. err is an output pin.
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 6 of 27 figure 7. 48-pin tsop i (12 18.4 1 mm) single chip enable with err cy7c1061ge [6, 7] package/grade id: zxi figure 8. 48-pin tsop i (12 18.4 1 mm) single chip enable without err cy7c1061g [6] package/grade id: zxi figure 9. 54-pin tsop ii (22.4 11 .84 1.0 mm) dual chip enable without err cy7c1061g [6] package/grade id: zsxi figure 10. 54-pin tsop ii (22.4 11.84 1.0 mm) dual chip enable with err cy7c1061ge [6, 7] package/grade id: zsxi pin configurations (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a 4 a 3 a 2 a 1 a 0 err ce i/o 0 i/o 1 i/o 2 i/o 3 v dd gnd i/o 4 i/o 5 i/o 6 i/o 7 we nc a 19 a 18 a 17 a 16 a 15 a 5 a 6 a 7 a 8 oe bhe ble i/o 15 i/o 14 i/o 13 i/o 12 gnd v dd i/o 11 i/o 10 i/o 9 i/o 8 nc a 9 a 10 a 11 a 12 a 13 a 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a 4 a 3 a 2 a 1 a 0 nc ce i/o 0 i/o 1 i/o 2 i/o 3 v dd gnd i/o 4 i/o 5 i/o 6 i/o 7 we nc a 19 a 18 a 17 a 16 a 15 a 5 a 6 a 7 a 8 oe bhe ble i/o 15 i/o 14 i/o 13 i/o 12 gnd v dd i/o 11 i/o 10 i/o 9 i/o 8 nc a 9 a 10 a 11 a 12 a 13 a 14 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 i/o 11 18 17 20 19 23 28 25 24 22 21 27 26 v ss i/o 10 i/o 12 v cc i/o 13 i/o 14 v ss a 16 a 17 a 11 a 12 a 13 a 14 i/o 0 a 15 i/o 7 i/o 9 v cc i/o 8 i/o 15 a 19 a 4 a 3 a 2 a 1 ce 1 v cc we ce 2 ble nc v ss oe a 8 a 7 a 6 a 5 a 0 nc a 9 bhe a 10 10 a 18 46 45 47 50 49 48 51 54 53 52 i/o 2 i/o 1 i/o 3 v ss v cc v ss i/o 6 i/o 5 v cc i/o 4 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 i/o 11 18 17 20 19 23 28 25 24 22 21 27 26 v ss i/o 10 i/o 12 v cc i/o 13 i/o 14 v ss a 16 a 17 a 11 a 12 a 13 a 14 i/o 0 a 15 i/o 7 i/o 9 v cc i/o 8 i/o 15 a 19 a 4 a 3 a 2 a 1 ce 1 v cc we ce 2 ble nc v ss oe a 8 a 7 a 6 a 5 a 0 err a 9 bhe a 10 10 a 18 46 45 47 50 49 48 51 54 53 52 i/o 2 i/o 1 i/o 3 v ss v cc v ss i/o 6 i/o 5 v cc i/o 4 notes 6. nc pins are not connected internally to the die. 7. err is an output pin.
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 7 of 27 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc relative to gnd ...................... ......................?0.5 v to +6.0 v dc voltage applied to outputs in high z state [8] ................................ ?0.5 v to v cc + 0.5 v dc input voltage [8] .............................. ?0.5 v to v cc + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (mil-std-883, method 3015) ................................. > 2001 v latch-up current .................................................... > 140 ma operating range grade ambient temperature v cc industrial ?40 ? c to +85 ? c 1.65 v to 2.2 v, 2.2 v to 3.6 v, 4.5 v to 5.5 v dc electrical characteristics over the operating range of ?40 ? c to 85 ? c parameter description test conditions 10 ns / 15 ns unit min typ [10] max v oh output high voltage 1.65 v to 2.2 v v cc = min, i oh = ?0.1 ma 1.4 ? ? v 2.2 v to 2.7 v v cc = min, i oh = ?1.0 ma 2.0 ? ? 2.7 v to 3.6 v v cc = min, i oh = ?4.0 ma 2.2 ? ? 4.5 v to 5.5 v v cc = min, i oh = ?4.0 ma 2.4 ? ? v ol output low voltage 1.65 v to 2.2 v v cc = min, i ol = 0.1 ma ? ? 0.2 v 2.2 v to 2.7 v v cc = min, i ol = 2 ma ? ? 0.4 2.7 v to 3.6 v v cc = min, i ol = 8 ma ? ? 0.4 4.5 v to 5.5 v v cc = min, i ol = 8 ma ? ? 0.4 v ih [8] input high voltage 1.65 v to 2.2 v 1.4 ? v cc + 0.2 v 2.2 v to 2.7 v 2.0 ? v cc + 0.3 2.7 v to 3.6 v 2.0 ? v cc + 0.3 4.5 v to 5.5 v 2.2 ? v cc + 0.5 v il [8] input low voltage 1.65 v to 2.2 v ?0.2 ? 0.4 v 2.2 v to 2.7 v ?0.3 ? 0.6 2.7 v to 3.6 v ?0.3 ? 0.8 4.5 v to 5.5 v ?0.5 ? 0.8 i ix input leakage current gnd < v in < v cc ?1.0 ? +1.0 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1.0 ? +1.0 ? a i cc operating supply current v cc = max, i out = 0 ma, cmos levels f = 100 mhz ? 90.0 110.0 ma f = 66.7 mhz ? 70.0 80.0 i sb1 automatic ce power down current ? ttl inputs max v cc , ce > v ih [9] , v in > v ih or v in < v il , f = f max ? ? 40.0 ma i sb2 automatic ce power down current ? cmos inputs max v cc , ce > v cc ? 0.2 v [9] , v in > v cc ? 0.2 v or v in < 0.2 v, f = 0 ? 20.0 30.0 ma notes 8. v il(min) = ?2.0 v and v ih(max) = v cc + 2 v for pulse durations of less than 2 ns. 9. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 10. typical values are included only for reference and are no t guaranteed or tested. typical values are measured at v cc = 1.8 v (for a v cc range of 1.65 v?2.2 v), v cc = 3 v (for a v cc range of 2.2 v?3.6 v), and v cc = 5 v (for a v cc range of 4.5 v?5.5 v), t a = 25 c.
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 8 of 27 capacitance parameter [11] description test conditions 54-pin tsop ii 48-ball vfbga 48-pin tsop i unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = v cc(typ) 10 10 10 pf c out i/o capacitance 10 10 10 pf thermal resistance parameter [11] description test conditions 54-pin tsop ii 48-ball vfbga 48-pin tsop i unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four layer printed circuit board 93.63 31.50 57.99 ? c/w ? jc thermal resistance (junction to case) 21.58 15.75 13.42 ? c/w ac test loads and waveforms figure 11. ac test loads and waveforms [12] 90% 10% v high gnd 90% 10% all input pulses v cc output 5 pf* * including jig and scope (b) r1 r2 ? rise time: fall time: > 1 v/ns (c) output 50 ? z 0 = 50 ? v th 30 pf* * capacitive load consists of all components of the test environment high-z characteristics: (a) > 1 v/ns parameters 1.8 v 3.0 v 5.0 v unit r1 1667 317 317 ? r2 1538 351 351 ? v th 0.9 1.5 1.5 v v high 1.8 3 3 v notes 11. tested initially and after any design or process changes that may affect these parameters. 12. full-device ac operation assumes a 100-s ramp time from 0 to v cc (min) and 100-s wait time after v cc stabilizes to its operational value.
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 9 of 27 data retention characteristics over the operating range of ?40 ? c to 85 ? c parameter description conditions min max unit v dr v cc for data retention 1.0 ? v i ccdr data retention current v cc = v dr , ce > v cc ? 0.2 v [13] , v in > v cc ? 0.2 v or v in < 0.2 v ?30.0ma t cdr [14] chip deselect to data retention time 0?ns t r [15] operation recovery time v cc > 2.2 v 10.0 ? ns v cc < 2.2 v 15.0 ? ns data retention waveform figure 12. data retention waveform [13] t cdr t r v dr = 1.0 v data retention mode v cc(min) v cc(min) v cc ce notes 13. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 14. tested initially and after any design or proces s changes that may affect these parameters. 15. full-device operation requires linear v cc ramp from v dr to v cc (min) > 100 ? s or stable at v cc (min) > 100 ? s.
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 10 of 27 ac switching characteristics over the operating range of ?40 ? c to 85 ? c parameter [16] description 10 ns 15 ns unit min max min max read cycle t power v cc (stable) to the first access [17] 100.0 ? 100.0 ? s t rc read cycle time 10.0 ? 15.0 ? ns t aa address to data / err valid ? 10.0 ? 15.0 ns t oha data / err hold from address change 3.0 ? 3.0 ? ns t ace ce low to data / err valid [18] ? 10.0 ? 15.0 ns t doe oe low to data / err valid ? 5.0 ? 8.0 ns t lzoe oe low to low-z [19, 20] 0?1.0? ns t hzoe oe high to high-z [19, 20] ? 5.0 ? 8.0 ns t lzce ce low to low-z [18, 19, 20] 3.0?3.0? ns t hzce ce high to high-z [18, 19, 20] ? 5.0 ? 8.0 ns t pu ce low to power-up [18, 21] 0?0? ns t pd ce high to power-down [18, 21] ? 10.0 ? 15.0 ns t dbe byte enable to data valid ? 5.0 ? 8.0 ns t lzbe byte enable to low-z [19,20] 0?1.0? ns t hzbe byte disable to high-z [19,20] ? 6.0 ? 8.0 ns write cycle [22, 23] t wc write cycle time 10.0 ? 15.0 ? ns t sce ce low to write end [18] 7.0 ? 12.0 ? ns t aw address setup to write end 7.0 ? 12.0 ? ns t ha address hold from write end 0? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 7.0 ? 12.0 ? ns t sd data setup to write end 5.0 ? 8.0 ? ns t hd data hold from write end 0 ? 0 ? ns t lzwe we high to low-z [19, 20] 3.0?3.0? ns t hzwe we low to high-z [19, 20] ? 5.0 ? 8.0 ns t bw byte enable to write end 7.0 ? 12.0 ? ns notes 16. test conditions assume signal transiti on time (rise/fall) of 3 ns or less, timing reference levels of 1.5 v (for v cc > 3 v) and v cc /2 (for v cc < 3 v), and input pulse levels of 0 to 3 v (for v cc > 3 v) and 0 to v cc (for v cc < 3v). test conditions for the read cycle use the output loading, sh own in part (a) of figure 11 on page 8 , unless specified otherwise. 17. t power gives the minimum amount of time that the power supply is at stable v cc until the first memory access is performed 18. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 19. t hzoe , t hzce , t hzwe , and t hzbe are specified with a load capacitance of 5 pf, as shown in part (b) of figure 11 on page 8 . hi-z, lo-z transition is measured ? 200 mv from steady state voltage. 20. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 21. these parameters are guaranteed by design and are not tested. 22. the internal write time of the memory is defined by the overlap of we = v il , ce = v il , and bhe or ble = v il . these signals must be low to initiate a write, and the high transition of any of these signals can terminate the opera tion. the input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 23. the minimum write pulse width for write cycle no. 2 (we controlled, oe low) should be sum of t hzwe and t sd .
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 11 of 27 switching waveforms figure 13. read cycle no. 1 of cy7c1061g (address transition controlled) [24, 25] figure 14. read cycle no. 2 of cy7c1061ge (address transition controlled) [24, 25] address data i/o previous data out valid data out valid t rc t oha t aa address data i/o previous data out valid data out valid t rc t oha t aa err previous err valid err valid t oha t aa notes 24. the device is continuously selected, oe = v il , ce = v il , bhe or ble or both = v il . 25. we is high for read cycle.
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 12 of 27 figure 15. read cycle no. 3 (oe controlled) [26, 27, 28] switching waveforms (continued) t rc t hzce t pd t ace t doe t lzoe t dbe t lzbe t lzce t pu high impedance data out valid high impedance address ce oe bhe/ ble data i/o v cc supply current t hzoe t hzbe i sb notes 26. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 27. we is high for read cycle. 28. address valid prior to or coincident with ce low transition.
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 13 of 27 figure 16. write cycle no. 1 (ce controlled) [29, 30, 31] figure 17. write cycle no. 2 (we controlled, oe low) [29, 30, 31, 32] switching waveforms (continued) address ce we bhe/ ble data i/o oe t wc t sce t aw t sa t pwe t ha t bw t hd t hzoe t sd data in valid note 33 address ce data i/o t wc t sce t hd t sd t bw bhe/ ble t aw t ha t sa t pwe t lzwe t hzwe we data in valid note 33 notes 29. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 30. the internal write time of the memo ry is defined by the overlap of we = v il , ce = v il and bhe or ble = v il . these signals must be low to initiate a write, and the high transition of any of these signals can terminate the operation. the input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 31. data i/o is in high impedance state if ce = v ih , or oe = v ih or bhe , and/or ble = v ih . 32. the minimum write cycle pulse width should be equal to sum of t hzwe and t sd . 33. during this period the i/os are in output state. do not apply input signals.
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 14 of 27 figure 18. write cycle no. 3 (we controlled) [34, 35, 36] switching waveforms (continued) address ce we bhe/ble data i/o oe t wc t sce t aw t sa t pwe t ha t bw t hd t hzoe t sd data in ? valid notes 34. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 35. the internal write time of the me mory is defined by the overlap of we = v il , ce = v il and bhe or ble = v il . these signals must be low to initiate a write, and the high transition of any of these signals ca n terminate the operation. the input data setup and hold timing should be referenced to the edge of the sig nal that terminates the write. 36. data i/o is in high-impedance state if ce = v ih , or oe = v ih or bhe , and/or ble = v ih . 37. during this period, the i/os are in ou tput state. do not apply input signals. note37
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 15 of 27 figure 19. write cycle no. 4 (ble or bhe controlled) [38, 39, 40] switching waveforms (continued) data in valid address ce we data i/o t wc t sce t aw t sa t bw t ha t hd t hzwe t sd bhe/ ble t pwe t lzwe note 41 notes 38. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 39. the internal write time of the memo ry is defined by the overlap of we = v il , ce = v il and bhe or ble = v il . these signals must be low to initiate a write, and the high transition of any of these signals can terminate the operation. the input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 40. data i/o is in high-impedance state if ce = v ih , or oe = v ih or bhe , and/or ble = v ih . 41. during this period, the i/os are in output state. do not apply input signals.
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 16 of 27 truth table ce [42] oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power hx [43] x [43] x [43] x [43] high-z high-z power down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high-z read lower bits only active (i cc ) l l h h l high-z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high-z write lower bits only active (i cc ) l x l h l high-z data in write upper bits only active (i cc ) l h h x x high-z high-z selected, outputs disabled active (i cc ) l x x h h high-z high-z selected, outputs disabled active (i cc ) err output ? cy7c1061ge output mode 0 read operation, no single-bit error in the stored data. 1 read operation, single-bit error detected and corrected. high-z device deselected or outputs disabled or write operation notes 42. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 43. the input voltage levels on t hese pins should be either at v ih or v il .
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 17 of 27 ordering code definitions ordering information speed (ns) voltage range ordering code package diagram package type (all pb-free) key features / differentiators operating range 10 2.2 v?3.6 v cy7c1061g30-10zxi 51-85183 48-pin tsop i (12 18.4 1.0 mm) single chip enable without err industrial cy7c1061ge30-10zxi single chip enable with err output at pin 6 cy7c1061g30-10zsxi 51-85160 54-pin tsop ii (22.4 11.84 1.0 mm) dual chip enable without err cy7c1061ge30-10zsxi dual chip enable with err output at pin 43 cy7c1061g30-10bvxi 51-85150 48-ball vfbga (6 8 1.0 mm) (pb-free) dual chip enable without err address msb a 19 at ball h6 cy7c1061ge30-10bvxi dual chip enable with err output at ball e3 address msb a 19 at ball h6 cy7c1061g30-10bv1xi single chip enable without err address msb a 19 at ball g2 cy7c1061g30-10bvjxi dual chip enable without err address msb a 19 at ball g2 15 1.65 v?2.2 v cy7c1061g18-15bv1xi single chip enable without err address msb a 19 at ball g2 industrial temperature range: i = industrial pb-free package type: xxx = zx or zsx or bvx zx = 48-pin tsop i; zsx = 54-pin tsop ii; bvx = 48-ball vfbga speed: xx = 10 ns or 15 ns voltage range: 18 = 1.65 v?2.2 v; 30 = 2.2 v?3.6 v; no character = 4.5 v?5.5 v err output single bit error indication revision code ?g?: process technology ? 65 nm data width: 1 = 16-bits density: 06 = 16-mbit family code: 1 = fast asynchronous sram family technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c cy 1 - xx i 7 06 g 1 xx x e xx
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 18 of 27 package diagrams figure 20. 48-pin tsop i (12 18.4 1.0 mm) z48a package outline, 51-85183 51-85183 *c
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 19 of 27 figure 21. 54-pin tsop ii (22.4 11. 84 1.0 mm) z54-ii p ackage outline, 51-85160 package diagrams (continued) 51-85160 *e
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 20 of 27 figure 22. 48-ball vfbga (6 8 1.0 mm) bv48/bz48 package outline, 51-85150 package diagrams (continued) 51-85150 *h
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 21 of 27 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package ttl transistor-transistor logic vfbga very fine-pitch ball grid array we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ? s microsecond ma milliampere mm millimeter ns nanosecond ? ohm % percent pf picofarad v volt w watt
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 22 of 27 errata this section describes the errata for the 16-mbit asynchronou s fast sram - cy7c1061g30 and cy7c1061ge30 - in 65-nm process technology. details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicabilit y. compare this document to the device?s datasheet for a complete functional description. if you have questions, contact your local cypress sales representative or raise a technical support case at www.cypress.com/go/support . part numbers affected fast sram [44] qualification status product status: all engineering samples ( note: reliability qualification is not complete. these samples are recommended to be used only for engineering builds and evaluation, and not for production builds). fast sram [44] errata summary this table defines the errata applicability to available 16-mbit devices. problem definition cy7c1061g30 and cy7c1061ge30 do not meet 10 ns speed in ac switching parameters as specified in ta b l e 1 . parameters affected ac switching parameters trigger condition functionality is not guaranteed when the device is operated at speed of 10 ns. scope of impact this issue may not pose problems for most end systems because they may incorporat e some margin to the dat asheet specifications. the deviation from the datasheet specified limit of 10 ns is 2 ns. workaround the ram controller timing needs additional margin to accommodate the slower speed. fix status the fix for the above issue is in progress. fixe d devices will be available from may 12, 2014. part number device characteristics cy7c1061g30 (all packages and options) 16-mbit fast sram cy7c1061ge30 (all packages and options) 16-mbit fast sram items part numbers silicon rev fix status fast sram [44] does not meet 10-ns speed -in ac switching parameters as specified in the datasheet specifications. cy7c1061g30 cy7c1061ge30 *a fixed devices to be available from may 12, 2014. note 44. this applies to all mpns mentioned in part numbers affected .
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 23 of 27 ac switching characteristics table 1. comparison of ac switching parameters for 10 ns and 12 ns parts parameter description -10 ns -12 ns unit min max min max read cycle t rc read cycle time 10 ? 12 ? ns t aa address to data valid ? 10 ? 12 ns t oha data hold from address change 3 ? 3 ? ns t ace ce low to data valid ? 10 ? 12 ns t doe oe low to data valid ? 5 ? 7 ns t lzoe oe low to low-z 1 ? 1 ? ns t hzoe oe high to high-z ? 5 ? 7 ns t lzce ce low to low-z 3 ? 3 ? ns t hzce ce high to high-z ? 5 ? 7 ns t pu ce low to power-up 0 ? 0 ? ns t pd ce high to power-down ? 10 ? 12 ns t dbe byte enable to data valid ? 5 ? 7 ns t lzbe byte enable to low-z 1 ? 1 ? ns t hzbe byte disable to high-z ? 6 ? 7 ns write cycle t wc write cycle time 10 ? 12 ? ns t sce ce low to write end 7 ? 9 ? ns t aw address setup to write end 7 ? 9 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 7 ? 9 ? ns t sd data setup to write end 5 ? 7 ? ns t hd data hold from write end 0 ? 0 ? ns t lzwe we high to low-z 3 ? 3 ? ns t hzwe we low to high-z ? 5 ? 7 ns t bw byte enable to end of write 7 ? 9 ? ns
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 24 of 27 document history page document title: cy7c1061g/cy7c1061ge, 16-mbit (1 m word s 16 bit) static ram with error-correcting code (ecc) document number: 001-81540 rev. ecn no. orig. of change submission date description of change ** 3690091 tava 07/27/2012 new data sheet. *a 3776318 aju 10/30/2012 updated document title to ?cy7c1061g/cy7c1061ge, 16-mbit (1 m words 16 bit) static ram with error-correcting code (ecc)?. updated features (highlighted typical i cc , included ecc feature). updated functional description (corrected typos, included 48-pin tsop i information). removed selection guide. added 48-ball vfbga pinouts ( figure 2 , figure 5 , and figure 6 ), added 48-pin tsop i ( figure 7 ), and 54-pin tsop ii ( figure 10 ). updated product portfolio to list all product options and added typical values for i cc and i sb2 parameters. changed latch up current limit from 200 to 140 ma (per jedec limits). updated dc electrical characteristics : changed maximum value of i cc parameter from 100 ma to 110 ma for the test condition f = 100 mhz. changed maximum value of i sb1 parameter from 30 ma to 40 ma. changed maximum value of i sb2 parameter from 25 ma to 30 ma. updated i sb2 test conditions to reflect correct cmos input levels. added note 9 and referred the same note in test conditions of i sb1 , i sb2 parameters. changed c in and c out values for 54 tsop and 48 bga packages from 6/8 pf to 10 pf. included 48-pin tsop i information in capacitance and thermal resistance . updated data retention characteristics changed maximum value of i ccdr parameter from 25 ma to 30 ma. added note 13 and referred the same note in test conditions of i ccdr parameter and figure 12 . updated ac switching characteristics : removed redundant t power parameter and associated footnote (captured in note 12 ). updated note 16 to include difference in input levels for v cc operation of less than 3 v. added note 18 . updated note 22 for better clarity. removed the note ?the minimum write cycle time for write cycle no. 2 (we controlled, oe low) is the sum of t hzwe and t sd .? and its references.
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 25 of 27 *a (cont.) 3776318 aju 10/30/2012 updated switching waveforms : updated note 24 for better clarity. updated figure 15 to make it applicable to both cy7c1061g and cy7c1061ge. updated note 26 for better clarity. updated note 28 to correct typos. referred notes 29 and 30 in figure 16 and figure 17 . referred notes 38 and 39 in figure 19 . updated notes 31 and 40 for better clarity. removed the note ?if ce goes high simultaneously with we going high, the output remains in a high-impedance state.? and its references (captured in note 31 and note 40 ). updated truth table (referred note 42 in ce column and added footnote 33). updated ordering information . updated package diagrams with the updated revisions. *b 4003550 aju 05/17/2013 no technical updates. *c 4042263 aju 06/27/2013 updated data retention characteristics : changed minimum value of v dr parameter from 1.5 v to 1 v. updated ac switching characteristics : changed maximum value of t hzbe parameter from 5 ns to 6 ns for 10 ns speed bin. changed minimum value of t sd parameter from 5.5 ns to 5 ns for 10 ns speed bin. *d 4120023 memj 09/11/2013 updated features : changed typical value of i sb2 from 10 ma to 20 ma. replaced ?1.5-v data retention? with ?1.0 v data retention?. updated data retention waveform : changed value of v dr from 1.5 v to 1 v. updated ac switching characteristics : changed minimum value of t lzoe parameter from 1 ns to 0 ns for 10 ns speed bin. changed minimum value of t lzbe parameter from 1 ns to 0 ns for 10 ns speed bin. updated ordering information (updated part numbers). added errata . updated in new template. document history page (continued) document title: cy7c1061g/cy7c1061ge, 16-mbit (1 m word s 16 bit) static ram with error-correcting code (ecc) document number: 001-81540 rev. ecn no. orig. of change submission date description of change
preliminary cy7c1061g/cy7c1061ge document number: 001-81540 rev. *k page 26 of 27 *e 4163557 memj 10/29/2013 updated pin configurations : added figure 3 . updated dc electrical characteristics : added minimum value of i sb2 parameter. added note 10 and referred the same note in minimum value of i sb2 parameter. updated ordering information : updated part numbers. updated details in ?key features / differentiators? column corresponding to mpn ?cy7c1061ge30-10bvxi? (corrected err output location from ball g2 to ball e3). *f 4272659 memj 02/05/2014 updated ac switching characteristics : added note 20 and referred the same note in description of t lzoe , t hzoe , t lzce , t hzce , t lzbe , t hzbe , t lzwe , t hzwe parameters. *g 4292074 memj / vini 03/07/2014 updated features section introduced 15-ns speed bin mentioned frequency for i cc typical measurement changed "an error detection" to "a single-bit error detection" updated dc electrical characteristics : added column for typical values moved reference to note 10 from i sb2 (typical) to the "typ" column heading updated ac switching characteristics : added t power and associated note 17. added note 23 and referred to write cycle timings referred note 19 to t hzbe and t lzbe added note 32 in figure 17 . added figure 18 (we controlled write) added note 33 in figure 16 and figure 17 , note 37 in figure 18 , and note 41 in figure 19 to indicate output state. added condition to place outputs in disable state by making both bhe and ble high in truth table . corrected err table by replacing ?no error in stored data? with ?no single bit error in stored data? clarified different ordering options with respect to with or without err, location of err, and address msb a 19 in ordering information . updated errata fix status *h 4330547 aju 04/02/2014 no content update. *i 4375287 aju 05/09/2014 updated errata : updated fast sram[44] errata summary : updated date in ?fix status? column in table and also ?fix status? in bulleted points below the table. completing sunset review. *j 4397546 vini 06/03/2014 updated footnote 19 - removed tlzoe, tlzce, tlzwe, and tlzbe, and added hi-z, lo-z transition. *k 4469360 nile 09/18/2014 updated package diagrams : spec 51-85160 ? changed revision from *d to *e. document history page (continued) document title: cy7c1061g/cy7c1061ge, 16-mbit (1 m word s 16 bit) static ram with error-correcting code (ecc) document number: 001-81540 rev. ecn no. orig. of change submission date description of change
document number: 001-81540 rev. *k revised september 18, 2014 page 27 of 27 qdr rams and quad data rate rams comprise a new family of products developed by cypress, idt, nec, renesas, and samsung. all pr oducts and company names mentioned in this document may be the trademarks of their respective holders. preliminary cy7c1061g/cy7c1061ge ? cypress semiconductor corporation, 2012-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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